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KAMHONG ELECTRONICS(HK) LIMITED
Http://www.kamhong.com.cn
RDA5800
SINGLE-CHIP BROADCAST FM RADIO TUNER
1 General Description
Rev.2.1-Mar.2007
The RDA5800 is a single-chip broadcast FM stereo radio tuner with fully integrated synthesizer, IF selectivity and MPX decoder. The tuner uses the CMOS process, support multi-interface and require the least external component. The package size is 4X4mm and is completely adjustment-free. All these make it very suitable for portable devices. The RDA5800 has a powerful low-IF digital audio processor, this make it have optimum sound quality with varying reception conditions. The RDA5800 can be tuned to the worldwide frequency band.
Figure 1-1. RDA5800 Top View
1.1
Features CMOS single-chip fully-integrated FM tuner Low power consumption Total current consumption lower than 16mA at 3.3V power supply Support worldwide frequency band 76 -108 MHz Digital low-IF tuner Image-reject down-converter High performance A/D converter IF selectivity performed internally Fully integrated digital frequency synthesizer Fully integrated on-chip RF and IF VCO Fully integrated on-chip loop filter Autonomous search tuning Support crystal oscillator Digital auto gain control (AGC) Digital adaptive noise cancellation Mono/stereo switch Soft mute 1.2 Applications Cellular handsets MP3, MP4 players Portable radios PDAs, Notebook PCs High cut Programmable de-emphasis (50/75 s) Receive signal strength indicator (RSSI) Bass boost Analog and digital volume control I2S digital output interface Line-level analog output voltage 32.768 KHz reference clock 2-wire and 3-wire serial control bus interface Directly support 32 resistance loading Integrated LDO regulator 2.7 to 5.5 V operation voltage 4X4mm 24 pin QFN package
Copyright (c) RDA Microelectronics Inc. 2006. All rights are reserved. The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA.
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RDA5800 FM Tuner V2.1
2
Table of Contents
General Description ....................................................................................................................................1 1.1 Features .........................................................................................................................................1 1.2 Applications ..................................................................................................................................1 2 Table of Contents.........................................................................................................................................2 3 Functional Description................................................................................................................................3 3.1 FM Receiver..................................................................................................................................3 3.2 Synthesizer ....................................................................................................................................3 3.3 Power Supply ................................................................................................................................4 3.4 Powerdown and Reset ...................................................................................................................4 3.5 Control Interface ...........................................................................................................................4 3.6 I2S Audio Data Interface ...............................................................................................................5 3.7 GPIO Outputs................................................................................................................................5 4 Electrical Characteristics ...........................................................................................................................6 5 Receiver Characteristics .............................................................................................................................7 6 Serial Interface ............................................................................................................................................8 6.1 Three-wire Interface Timing .........................................................................................................8 6.2 I2C Interface Timing......................................................................................................................9 7 Register Definition ....................................................................................................................................10 8 Pins Description.........................................................................................................................................12 9 Application Diagram.................................................................................................................................13 9.1 Audio Loading Resistance Larger than 32: ..............................................................................13 9.1.1 Bill of Materials: .........................................................................................................................13 9.2 Audio Loading Resistance Lower than 32: ..............................................................................14 9.2.1 Bill of Materials: .........................................................................................................................14 9.3 Audio Loading Resistance Larger than 32: ..............................................................................15 9.3.1 Bill of Materials: .........................................................................................................................15 10 Package Physical Dimension ....................................................................................................................16 11 Change List................................................................................................................................................17 12 Notes .......................................................................................................................................................17 13 Contact Information .................................................................................................................................17
1
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RDA5800 FM Tuner V2.1
3
Functional Description
I PGA
LNAP LNAN LNA +
I ADC
Audio DSP Core
digital filter MPX decoder stereo/mono audio
L DAC
LOUT
0/90
Limiter
Q PGA
Q ADC
R DAC
ROUT
32.768 KHz RCLK DVDD 2.7-5.5 V AVDD
VCO Synthesizer RSSI LDO
GPIO
GPIO RST SEN
Interface Bus
SCLK SDIO VIO
MCU
Figure 3-1. RDA5800 FM Tuner Block Diagram 3.1 FM Receiver The PGA amplifies the mixer output IF signal and then digitized with ADCs. The DSP core finishes the channel selection, FM demodulation, stereo MPX decoder and output audio signal. The MPX decoder can autonomous switch from stereo to mono to limit the output noise. The DACs convert digital audio signal to analog and change the volume at same time. The DACs has low-pass feature and -3dB frequency is about 30 KHz. 3.2 Synthesizer
The receiver uses a digital low-IF architecture that avoids the difficulties associated with direct conversion while delivering lower solution cost and reduces complexity, and integrates a low noise amplifier (LNA) supporting the FM broadcast band (76 to 108MHz), a quadrature image-reject mixer, a programmable gain control (PGA), a high resolution analog-to-digital converters (ADCs), an audio DSP and a highfidelity digital-to-analog converters (DACs). The LNA has differential input ports (LNAP and LNAN) and supports any input port by set according registers bits (LNA_PORT_SEL[1:0]). The LNA default input resistance is 150 Ohm under single or dual input mode. It default input common mode voltage is GND. The limiter prevents overloading and limits the amount of intermodulation products created by strong adjacent channels. The quadrature mixer down converts the LNA output differential RF signal to low-IF, it also has image-reject function.
The frequency synthesizer generates the local oscillator signal which divide to quadrature, then be used to downconvert the RF input to a constant low intermediate frequency (IF). The synthesizer reference clock is 32.768 KHz. The synthesizer frequency is defined by bits CHAN[9:0] with the range from 76MHz to 108MHz.
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RDA5800 FM Tuner V2.1
3.3
Power Supply
Parameter Symbol Test Condition
SEN Input to RST
Min
Typ
Max
Unit
The RDA5800 integrated one LDO which supplies power to the chip. The external supply voltage range is 2.7-5.5 V. 3.4 Powerdown and Reset
Setup Hold
tsrst thrst
30 30
ns ns
SEN Input to RST
The RDA5800 selects three-wire or I2C control interface in reset process. Setting RST pin low after power up will reset the chip to initial state. Setting RST pin high will bring the chip out of reset. Setting SEN low on the rising edge of RST will select three-wire control interface, and setting SEN high on the rising edge of RST will select I2C control interface.
Table 3-2 I2C Reset Timing Characteristics
When need, the RDA5800 could enter into a powerdown mode to reduce power consumption, with software setting the ENABLE bit low. In powerdown mode, analog and digital circuitry are both disabled, while maintaining register configuration and keeping control interface active. The RDA5800 could enter back into normal mode by setting the ENABLE bit high, and resume normal working. Details refer to RDA5800 Programming Guide. 3.5 Control Interface
Figure 3-1. Three-wire Interface Reset Timing Diagram
The RDA5800 supports three-wire and I2C control interface. User could select either of them to program the chip. The three-wire interface is a standard SPI interface. It includes three pins: SEN, SCLK and SDIO. Each register write is 25-bit long, including 4-bit high register address, a r/w bit, 4-bit low register address, and 16-bit data (MSB is the first bit). RDA5800 samples command byte and data at posedge of SCLK. Each register read is also 25-bit long, including 4-bit high register address, a r/w bit, 4-bit low register address, and 16-bit data (MSB is the first bit) from RDA5800. The turn around cycle between command byte from MCU and data from RDA5800 is a half cycle. RDA5800 samples command byte at posedge of SCLK, and output data also at posedge of SCLK. The I2C interface is compliant to I2C Bus Specification 2.1. It includes two pins: SCLK and SDIO. A I2C interface transfer begins with START condition, a command byte and data bytes, each byte has a followed ACK (or NACK) bit, and ends with STOP condition. The command byte includes a 7-bit chip address (0010000b) and a R/W bit. The ACK (or NACK) is always sent out by receiver. When in write transfer, data bytes is written out from MCU, and when in read transfer, data bytes is read out from RDA5800. There is no visible register address in I2C interface transfers. The I2C interface has a fixed start register address (0x02h
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SEN Input to RST
Setup Hold
tsrst thrst
30 30
ns ns
SEN Input to RST
Table 3-1 SPI Reset Timing Characteristics
Figure 3-2. I2C Interface Reset Timing Diagram
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RDA5800 FM Tuner V2.1
0x0Ah for read transfer), and an internal incremental address counter. If register address meets the end of register file, 0x3Ah, register address will wrap back to 0x00h. For write transfer, MCU programs registers from register 0x02h high byte, then register 0x02h low byte, then register 0x03h high byte, till the last register. RDA5800 always gives out ACK after every byte, and MCU gives out STOP condition when register programming is finished. For read transfer, after command byte from MCU, RDA5800 sends out register 0x0Ah high byte, then register 0x0Ah low byte, then register 0x0Bh high byte, till receives NACK from MCU. MCU gives out ACK for data bytes besides last data byte. MCU gives out NACK for last data byte, and then RDA5800 will return the bus to MCU, and MCU will give out STOP condition. Details refer to RDA5800 Programming Guide. 3.6 I2S Audio Data Interface
audio interface. The interface is fully compliant with I2S bus specification. When setting I2SEN bit high, RDA5800 will output SCK, WS, SD signals from GPIO3, GPIO1, GPIO2 as I2S master and transmitter, the sample rate is 42Kbps. 3.7 GPIO Outputs
The RDA5800 has three GPIOs. The function of GPIOs could programmed with bits GPIO1[1:0], GPIO2[1:0], GPIO3[1:0] and I2SEN. If I2SEN is set to low, GPIO pins could be programmed to output low or high or high-Z, or be programmed to output interrupt and stereo indicator with bits GPIO1[1:0], GPIO2[1:0], GPIO3[1:0]. GPIO2 could be programmed to output a low interrupt (interrupt will be generated only with interrupt enable bit STCIEN is set to high) when seek/tune process completes. GPIO3 could be programmed to output stereo indicator bit ST. Constant low, high or high-Z functionality is available regardless of the state of VA and VD supplies or the ENABLE bit.
The RDA5800 supports I2S (Inter_IC Sound Bus)
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RDA5800 FM Tuner V2.1
4
Electrical Characteristics
DC Electrical Specification (Recommended Operation Conditions):
DESCRIPTION Analog Supply Voltage Digital Supply Voltage Interface Supply Voltage Ambient Temperature CMOS Low Level Input Voltage CMOS High Level Input Voltage CMOS Threshold Voltage MIN 2.7 2.7 1.5 -20 0 0.7*VDD 0.5*VDD TYP 3.3 3.3 27 MAX 5.5 5.5 3.6 +70 0.3*DVDD DVDD UNIT V V V V V V
Table 4-1
SYMBOL
AVDD DVDD VIO Tamb VIL VIH VTH
Table 4-2
SYMBOL
DC Electrical Specification (Absolute Maximum Ratings):
DESCRIPTION Interface Supply Voltage Ambient Temperature Input Current Input Voltage
(1) (1)
MIN -0.5 -40 -10 -0.3
TYP
MAX +4 +90 +10 VIO+0.3 -20
UNIT V C mA V dBm
VIO Tamb IIN VIN Vlna
Notes:
LNA FM Input Level 1. For Pin: SCLK, SDIO, SEN, RST.
Table 4-3
Power Consumption Specification
(VDD = 2.7 to 5.5 V, TA = -25 to 85 , unless otherwise specified) SYMBOL DESCRIPTION Analog Supply Current Digital Supply Current Interface Supply Current Analog Powerdown Current Digital Powerdown Current CONDITION ENABLE=1 ENABLE=1 SCLK and RCLK inactive ENABLE=0 ENABLE=0 TYP 13 3 1 2 2 UNIT mA mA A A A
IA ID IVIO IAPD IDPD
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RDA5800 FM Tuner V2.1
5
Receiver Characteristics
Receiver Characteristics
Table 5-1
(VDD = 2.7 to 5.5 V, TA = -25 to 85 C, unless otherwise specified) SYMBOL PARAMETER CONDITIONS BAND=0 BAND=1 (S+N)/N=26dB
7 7
MIN 87.5 76
TYP
MAX 108 91
UNIT MHz MHz V EMF pF dBV dB dB mV
General specifications
Fin Vrf Rin Cin IP3in
FM Input Frequency Sensitivity
1,2,3
1.5 130 2 150 4 -
2 170 6 -
LNA Input Resistance Input IP3
4
LNA Input Capacitance
1,2
AGCD=1 m=0.3 200KHz Volume_dsp[3:0]=1111 Volume_dac[3:0] =1111
80 40 45 60 75
am
S200 VAFL; VAFR
AM Suppression
Adjacent Channel Selectivity Left and Right Audio Frequency Output Voltage (Pins LOUT and ROUT) Maximum Signal Plus Noise to Noise Ratio
1,2,3,5
90
(S+N)/N
54 35
60 0.3
0.5 1
dB dB % dB
SCS
THD
Stereo Channel Separation Audio Total Harmonic Distortion
1,3,6
AOI
RL
Audio Output L/R Imbalance Audio Output Loading Resistance Pins LNAN and LNAP Input Common Mode Voltage Audio Output Common Mode Voltage8 Pins NC (22, 23) Common Mode Voltage 0.9 0.45 Single-ended 32 -
-
Pins LNAN, LNAP, LOUT, ROUT and NC(22,23)
Vcom_rfin Vcom Vcom_nc
Float
V 1.1 0.55 V V
1 0.5
! The NC(22, 23) pins SHOULD BE left floating. Notes: 1. Fin=76 to 108MHz; Fmod=1KHz; de-emphasis=75s; MONO=1; L=R unless noted otherwise; 2. f=22.5KHz; 3. BAF = 300Hz to 15KHz, RBW <=10Hz; 4. |f2-f1|>1MHz, f0=2xf1-f2, AGC disable, Fin=76 to 108MHz; 5. PRF=60dBUV; 6. f=75KHz. 7. Measured at VEMF = 1 m V, f RF = 76 to 108MHz 8. At LOUT and ROUT pins
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RDA5800 FM Tuner V2.1
6
6.1
Serial Interface
Three-wire Interface Timing
Table 6-1
Three-wire Interface Timing Characteristics
(VDD = 2.7 to 5.5 V, TA = -25 to 85 C, unless otherwise specified) PARAMETER SCLK Cycle Time SCLK Rise Time SCLK Fall Time SCLK High Time SCLK Low Time SDIO Input, SEN to SCLK Setup SDIO Input, to SCLK Hold SCLK to SDIO Output Valid SEN to SDIO Output High Z Digital Input Pin Capacitance SYMBOL TEST CONDITION MIN 35 50 50 10 10 10 10 Read Read 2 2 10 10 5 TYP MAX UNIT ns ns ns ns ns ns ns ns ns pF
tCLK tR tF tHI tLO ts th tcdv tsdz
Figure 6-1. Three-wire Interface Write Timing Diagram
Figure 6-2. Three-wire Interface Read Timing Diagram
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RDA5800 FM Tuner V2.1
6.2
I2C Interface Timing
Table 6-2
I2C Interface Timing Characteristics
(VDD = 2.7 to 5.5 V, TA = -25 to 85 C, unless otherwise specified) PARAMETER SCLK Frequency SCLK High Time SCLK Low Time Setup Time for START Condition Hold Time for START Condition Setup Time for STOP Condition SDIO Input to SCLK Setup SDIO Input to SCLK Hold STOP to START Time SDIO Output Fall Time SDIO Input, SCLK Rise/Fall Time Input Spike Suppression SCLK, SDIO Capacitive Loading Digital Input Pin Capacitance SYMBOL TEST CONDITION MIN 0 0.6 1.3 0.6 0.6 0.6 100 0 1.3 20+0.1Cb 20+0.1Cb TYP MAX 400 900 250 300 50 50 5 UNIT KHz s s s s s ns ns s ns ns ns pF pF
fscl thigh tlow tsu:sta thd:sta tsu:sto tsu:dat thd:dat tbuf tf:out tr:in / tf:in tsp Cb
Figure 6-3. I2C Interface Write Timing Diagram
Figure 6-4. I2C Interface Read Timing Diagram
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RDA5800 FM Tuner V2.1
7
Register Definition
BITS 15:8 15 14 13 12 9 8 DHIZ DMUTE MONO BASS SEEKUP SEEK NAME CHIPID[7:0] Chip ID. Audio Output High-Z Disable. 0 = High impedance; 1 = Normal operation Mute Disable. 0 = Mute; 1 = Normal operation Mono Select. 0 = Stereo; 1 = Force mono Bass Boost. 0 = Disabled; 1 = Bass boost enabled Seek Up. 0 = Seek down; 1 = Seek up Seek. 0 = Disable; 1 = Enable Seek begins in the direction specified by SEEKUP and ends when a channel is found with RSSI level above SEEKTH[5:0], or the entire band has been searched. The SEEK bit is set low and the STC bit is set high when the seek operation completes. Power Up Enable. 0 = Disabled; 1 = Enabled Channel Select. BAND = 0 Frequency = Channel Spacing (kHz) x CHAN+ 87.5 MHz BAND = 1 Frequency = Channel Spacing (kHz) x CHAN + 76.0 MHz CHAN is updated after a seek operation. Channel Spacing. 0 = see SPACE bit; 1 = 50 kHz Band Select. 0 = 87.5-108 MHz (US/Europe) 1 = 76-91 MHz (Japan) Channel Spacing. 0 = 100 kHz; 1 = 200 kHz Seek/Tune Complete Interrupt Enable. 0 = Disable Interrupt; 1 = Enable Interrupt Setting STCIEN = 1 will generate a 5 ms low pulse on GPIO2 when the interrupt occurs. De-emphasis. 0 = 75 s; 1 = 50 s I2S Bus Enable. 0 = disabled; 1 = enabled. General Purpose I/O 3. 00 = High impedance 01 = Mono/Stereo indicator (ST) FUNCTION 0 0 0 0 0 0 DEFAULT 0x58
REG 00H 02H
0 03H 15:8
ENABLE CHAN[7:0]
0 0x00
2 1
SPACE_50K BAND
0 0
0 04H 14
SPACE STCIEN
0 0
11 6 5:4
DE I2SEN GPIO3[1:0]
0 0 00
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RDA5800 FM Tuner V2.1 FUNCTION 10 = Low 11 = High General Purpose I/O 2. 00 = High impedance 01 = Interrupt (INT) 10 = Low 11 = High General Purpose I/O 1. 00 = High impedance 01 = Reserved 10 = Low 11 = High INT Mode Select. 0 = Generate 5ms interrupt; 1 = Interrupt last until write action occurs. Seek Threshold in Logarithmic. 000000 = min RSSI; 111111 = max RSSI DSP Volume Control. 0000=min -15db; 1111=max 0db DAC Gain Control Bits (Volume). 0000=min; 1000=max Volume scale is logarithmic Seek/Tune Complete. 0 = Not complete; 1 = Complete The seek/tune complete flag is set when the seek or tune operation completes. Seek Fail. 0 = Seek successful; 1 = Seek failure The seek fail flag is set when the seek operation fails to find a channel with an RSSI level greater than SEEKTH[5:0]. Stereo Indicator. 0 = Mono; 1 = Stereo Stereo indication is available on GPIO3 by setting GPIO1[1:0] =01. Read Channel. BAND = 0 Frequency = Channel Spacing (kHz) x READCHAN + 87.5 MHz BAND = 1 Frequency = Channel Spacing (kHz) x READCHAN + 76.0 MHz READCHAN is updated after a tune or seek operation. RSSI in Logarithmic. 000000 = min; 111111 = max LNA input port selection bit. 01 = LNAN input 10 = LNAP input 11 = dual port input DEFAULT
REG
BITS
NAME
3:2
GPIO2[1:0]
00
1:0
GPIO1[1:0]
00
05H
15
INTMODE
0
13:8 7:4 3:0
SEEKTH[5:0] VOLUME_DSP[3:0] VOLUME_DAC[3:0]
000100 1111 0000
0AH
14
STC
0
13
SF
0
8
ST
1
7:0
READCHAN[7:0]
0x00
0BH 10H
13:8 14:13
RSSI LNA_PORT_SEL[1:0]
0x00 10
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RDA5800 FM Tuner V2.1
8
Pins Description
Figure 0-1. RDA5800 Top View
Table 0-1
GND LNAN,LNAP RFGND XTAL RST SEN SCLK SDIO RCLK VIO AVDD ROUT,LOUT DVDD
RDA5800 Pins Description
PIN DESCRIPTION
SYMBOL
1,5,14,17,24 2,4 3 6 7 8 9 10 11 12 13 15,16 18 19,20,21 22,23
Ground. Connect to ground plane on PCB LNA input port. For single-ended input, LNAN should be connected to RFGND LNA ground. Connect to ground plane on PCB Crystal oscillator input. Latch reset (active low) input for serial control bus Latch enable (active low) input for serial control bus Clock input for serial control bus Data input/output for serial control bus 32.768KHz external reference clock input Power supply for I/O Power supply for analog section Right/Left audio output Power supply for digital section General purpose input/output No Connect
GPIO1,GPIO2,GPIO3 NC
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RDA5800 FM Tuner V2.1
9
9.1
Application Diagram
Audio Loading Resistance Larger than 32:
Notes: 1. J1: Common 32 Resistance Headphone; 2. U1: RDA5800 Chip; 3. R1,R2 I2C 3-wire Bus Pull-up
19
GND GPIO1 GPIO2 GPIO3
Resistor; 4. V1: Analog and Digital Power Supply (2.7~5.5V); 5. FM Choke (L3 and C3) for Audio Common and LNA Input Common; 6. Pins NC(22, 23),XTAL Should
NC
SCLK
NC
RCLK
SDIO
RST
SEN
VIO
be Leaved Floating; 7. Place C6 Close to AVDD pin.
Figure 9-1. RDA5800 FM Tuner Application Diagram (TCXO Application)
9.1.1
Bill of Materials:
VALUE DESCRIPTION SUPPLIER
COMPONENT
U1 J1 R1,R2 L3/C3 C4,C5 C6
RDA5800 10K 100nH/24pF 125F 24nF
7
Broadcast FM Radio Tuner Common 32 Resistance Headphone I2C Bus Pull-up Resistor LC Chock for LNA Input Audio AC Couple Capacitors Power Supply Bypass Capacitor
RDA
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RDA5800 FM Tuner V2.1
9.2
Audio Loading Resistance Lower than 32:
Notes: 1. J1: Resistance Lower than 32 Audio Speaker or Headphone 2. U1: RDA5800 Chip 3. R1,R2 I2C 3-wire Bus Pull-up Resistor 4. V1: Analog and Digital Power Supply (2.7~5.5V) 5. FM Choke (L3 and C3) for Audio Common and LNA Input Common 6. Pins NC(22, 23),XTAL Should be Leaved Floating 7. Place C6 Close to AVDD pin 8. Changing the Resistor R4 and R5 Value can Change the Output Volume.
Figure 9-2. RDA5800 FM Tuner Application Diagram (Audio Amplifier Application) 9.2.1 Bill of Materials:
VALUE DESCRIPTION SUPPLIER
COMPONENT
U1 U2 J1 R1,R2 L1/C1; L2/C2 L3/C3 C6 R4,R5 R2/C7; R3/C8
RDA5800
Broadcast FM Radio Tuner Audio Amplifier Audio Speaker
RDA
10K 100nH/24pF 100nH/24pF 24nF 20K 20K/0.39F
I2C Bus Pull-up Resistor LC Chock for Audio Output LC Chock for LNA Input Power Supply Bypass Capacitor Audio Amplifier Feedback Resistors Audio High-passed Filter and Amplifier Input Resistors
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RDA5800 FM Tuner V2.1
9.3
Audio Loading Resistance Larger than 32:
Notes: 1. J1: Common 32 Resistance Headphone; 2. U1: RDA5800 Chip; 3. U2: 32.768KHz Crystal oscillator 4. R1,R2: I2C 3-wire Bus Pull-up Resistor; 4. V1: Analog and Digital Power Supply (2.7~5.5V); 5. FM Choke (L3 and C3) for Audio Common and LNA Input Common; 6. Pins NC(22, 23) Should be Leaved Floating; 7. Place C6 Close to AVDD pin. 8.Load of Crystal oscillator (C6,C7,R3,R2) 9. Place U2 Close to U1
Figure 9-3. RDA5800 FM Tuner Application Diagram (DCXO Application)
9.3.1
Bill of Materials:
VALUE DESCRIPTION SUPPLIER
COMPONENT
U1 U2 J1 R1,R2 L3/C3 C4,C5 C2 C6,C7 R3,R4
RDA5800 DCXO 10K 100nH/24pF 125F 24nF 22pF 5M/250K
Broadcast FM Radio Tuner Crystal oscillator 32.768KHz Common 32 Resistance Headphone I2C Bus Pull-up Resistor LC Chock for LNA Input Audio AC Couple Capacitors Power Supply Bypass Capacitor Load Capacitor of DCXO Load Resistor f DCXO
RDA
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RDA5800 FM Tuner V2.1
10 Package Physical Dimension
Figure 10-1 illustrates the package details for the RDA5800. The package is lead-free and RoHS-compliant.
MIN
D E
NOM 4.00 BSC 4.00 BSC
MAX
D2 E2
e
2.00 2.00 0.30 0.18 0.80 0.00
2.15 2.15 0.50 BSC 0.40 0.25 0.90 0.02 0.20 ref
2.25 2.25 0.50 0.30 1.00 0.05
L b A A1 A3
Figure 10-2. 24-Pin 4x4 Quad Flat No-Lead (QFN)
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RDA5800 FM Tuner V2.1
11 Change List
REV DATE AUTHER CHANGE DESCRIPTION
V1.0 V2.0 V2.1 V2.2
2006-11-28 2007-03-08 2007-03-18 2007-04-23
Chun Zhao, Lin Li, Hua Li Chun Zhao, XiaoQi You XiaoQi You XiaoQi You
Original Draft. Up data test result; add DCXO application Up data Package Physical Dimension Add Table 3-1,3-2; Up data Application Diagram, Add Pull-Up Resister R2; Add note 4;
12 Notes
1 I 2 C Pin /SEN Pin VIO 2 S i47 00 p in t o p in 1 Pin6 XTAL 2 10H b i t [1 4 :13 ] L na_ por t _s e l [1 : 0 ] , 3 RDA5800 32.768KHz crystal oscillator 9-3 4: I2C
I2C
13 Contact Information
KAMHONG ELECTRONICS(HK) LIMITED
Tel: Fax: 0755-86120627 0755-26442180
Mobile:13642349565 Http://www.kamhong.com.cn
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RDA5800 FM Tuner V2.1
Copyright (c) RDA Microelectronics Inc. 2006. All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 18 of 18

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